The present invention relates to a semiconductor integrated circuit which contains a logic gate and a logic combinatorial circuit, and more particularly, it relates to a semiconductor integrated circuit with low power consumption.
The power consumption in a semiconductor integrated circuit which contains a transfer gate and a logic combinatorial circuit is generally in proportion to a frequency of switching a logic gate included in the circuit and an electrostatic capacity of a node to be switched, and is also in proportion to a square of the switching amplitude. In this case, the switching amplitude is known to be equal to a supply voltage in an ordinary CMOS semiconductor integrated circuit.
Accordingly, in an attempt to decrease the power consumption in the semiconductor integrated circuit, one of the following measures should be adopted: the frequency of switching the logic gate is decreased in the step of system architecture; the capacitance of the switching node is decreased through some means in processing or designing a mask; a circuit operatable at a low voltage is somehow realized; and two or more of these measures are appropriately combined. Among these measures, the decrease of the operating voltage of the circuit can be regarded to be the most and directly effective in the decrease of power consumption because power consumption is in proportion to the square of the supply voltage.
On the other hand, it is known that power consumption can be largely decreased, not by merely decreasing the supply voltage for the circuit, bug by optimizing the parallelism and the operation cycle time of the circuit, a supply voltage and a threshold voltage of a transistor. For example, it is described that power reduction of several factors of ten can be obtained by decreasing a supply voltage and increasing the parallelism of the circuit without sacrificing the circuit performance in "Trading Speed for Low Power by Choice of Supply and Threshold Voltages" (Duke Liu, et al., IEEE Journal of Solid-State Circuits, Vol. 28, No. 1, January 1993, pp. 10-17).
There arises the following problems, however, in the attempt to decrease a supply voltage in the aforementioned conventional manner.
First, as a supply voltage is decreased, power consumption is decreased, while the delay time of a logic gate is increased. As the delay time is increased, the delay time depends more and more upon the load capacitance. It is, however, difficult to accurately estimate the load capacitance, and hence, it becomes relatively difficult to realize a low timing skew. Furthermore, when a clock system is designed using a low speed logic gate, the ramp of a waveform transferred within the integrated circuit is increased, the delay time value (i.e., clock skew) is also increased due to the change of the internal waveform caused by the variation of the process conditions, and the deviation of the delay time becomes larger. Therefore, the circuit is easily affected by the variation in the processes, resulting in a difficulty in realizing a circuit with a high yield. In addition, when the waveforms transferred within the logic circuit is ramped, a malfunction due to the effect of superimposed noise tends to occur more frequently.
In order to obtain an integrated circuit without a malfunction, it is necessary to minimize a phase difference (which is designated as a timing skew) among control signals and clocks interconnected as a network in the integrated circuit, and to accurately estimate the phase difference in the step of the design of the integrated circuit. It is well known that a small timing skew can be obtained by using a high speed logic gate in which a delay time is minimally varied by the change of the load capacitance. It is, however, difficult to simultaneously satisfy the two demands, i.e., the operation at a low voltage and a low timing skew, in the above described semiconductor integrated circuit.
Secondly, as a supply voltage is decreased, the deviation of the threshold voltage of a transistor more largely affects the delay time. This effect becomes more noticeable when the supply voltage for the integrated circuit approximates the threshold voltage of the transistor.
Thirdly, it is difficult to use an N-channel MOS transistor with a smaller layout area as a transfer gate in a logic circuit operated at a low voltage. When a logic gate using a transfer gate as the input is utilized, the output voltage is decreased by a voltage equal to the threshold voltage of the transfer gate, as the supply voltage is decreased. Accordingly, it becomes difficult to secure the margin of the output voltage of the transfer gate against the logic threshold voltage, resulting in a difficulty in realizing a high speed and definite operation of the circuit. Thus, an N-channel MOS transistor cannot be used as a transfer gate. Moreover, with regard to the supply voltage, the circuit cannot be operated around the threshold voltage of the transistor. Therefore, in order to avoid this problem of the output voltage of the transfer gate in a circuit operating at a low voltage, a complementary transfer gate in which a P-channel transistor and an N-channel transistor is connected in parallel is generally used. Such a complementary transfer gate, however, requires an extra transistor and a complementary control signal, and as a result, the usage of the complementary transfer gate capacitance of the transistor is also increased, the decrease of the logic transfer speed caused by the low voltage operation is further accelerated.
In this manner, a conventional semiconductor integrated circuit which contains a logic combinatorial circuit and a transfer gate has mainly the aforementioned three problems that are related to one another. As a result, it has been difficult to decrease power consumption in such an integrated circuit.